maruel
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maruel got a reaction from jscax in [RfC] Make Armbian more IoT friendly?Context: I implemented a GPIO driver in Golang for A64 running armbian using memory mapped registers leveraging /dev/mem. Will test on H3 as soon as I receive my board. The main improvement over sunxi-pio is that I implemented edge based triggering leveraging sysfs gpio, since interrupts are not accessible in user mode yet polling sucks.
I realized the /dev/gpiomem concept (at least as implemented by Raspbian) is not applicable on (some) Allwinner processors (at least on A64 and H3) because they require 2 separate sections to be memory mapped to access all the pins. GPIO belonging to group PB to PH use the registers located at 0x01C20800 and group PL uses registers located at 0x01F02C00. So I'll forget on this gpiomem idea for now. And since Pine64 has PL pins on its PI2 header, it's really important to be able to access this group.
That's annoying as this requires me to run my app as root for the foreseeable future, which is really a downer.
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<random rant>
Allwinner CPUs has only a subset of pins supporting edge based triggering: in groups PB, PG, PH and PL, unlike bcm283x which supports it on all pins. On the other hand, you can query the current pull resistor on any pin on Allwinner, unlike bcm283x which is a black box. You can't have it all...
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maruel got a reaction from tkaiser in [RfC] Make Armbian more IoT friendly?Context: I implemented a GPIO driver in Golang for A64 running armbian using memory mapped registers leveraging /dev/mem. Will test on H3 as soon as I receive my board. The main improvement over sunxi-pio is that I implemented edge based triggering leveraging sysfs gpio, since interrupts are not accessible in user mode yet polling sucks.
I realized the /dev/gpiomem concept (at least as implemented by Raspbian) is not applicable on (some) Allwinner processors (at least on A64 and H3) because they require 2 separate sections to be memory mapped to access all the pins. GPIO belonging to group PB to PH use the registers located at 0x01C20800 and group PL uses registers located at 0x01F02C00. So I'll forget on this gpiomem idea for now. And since Pine64 has PL pins on its PI2 header, it's really important to be able to access this group.
That's annoying as this requires me to run my app as root for the foreseeable future, which is really a downer.
---
<random rant>
Allwinner CPUs has only a subset of pins supporting edge based triggering: in groups PB, PG, PH and PL, unlike bcm283x which supports it on all pins. On the other hand, you can query the current pull resistor on any pin on Allwinner, unlike bcm283x which is a black box. You can't have it all...
