Setup clock hierarchy for I2S in device tree

Hi,

I need to help for understandable how set right clock hierarchy for i2s bus with external master-clock signal. This mode supported rockchip processors (RK3328, RK3399) but there are very small information how it can do.
Today we have out of box in armbian for Nanopi Neo3 working I2S with master-clock from PLL, but I want change master-clock source from PLL to external signal. In souce and clock debugfs I find that I2S1 ("i2s1_pre") can be clocked from 4 sources: clk_i2s1_div, clk_i2s1_frac, clkin_i2s1, xin12m. By default parent for i2s1_pre set to clk_i2s1_div, which have parent cpll. Hence we must change parent for i2s1_pre to clkin_i2s1, but clock clkin_i2s1 not exists. OK, I added clkin_i2s1 through overlay:

/dts-v1/;
/plugin/;

/ {
    compatible = "friendlyelec,nanopi-neo3", "rockchip,rk3328";

    fragment@0 {
        target-path = "/";
        __overlay__ {
            clk_i2s1: clk_i2s1 {
                    compatible = "fixed-clock";
                    #clock-cells = <0>;
                    clock-output-names = "clk_i2s1";
                    clock-frequency = <22579200>;
            };
        };
    };
};

and I see clkin_i2s1 in clock summary (fragments😞

                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 xin24m                              10       10        0    24000000          0     0  50000         Y
    pll_cpll                          1        1        0  1200000000          0     0  50000         Y
       cpll                           8       13        0  1200000000          0     0  50000         Y
          clk_i2s1_div                0        0        0    75000000          0     0  50000         N
             i2s1_pre                 0        0        0    75000000          0     0  50000         Y
                clk_i2s1              0        0        0    75000000          0     0  50000         N
                   i2s1_out           0        0        0    75000000          0     0  50000         N
             clk_i2s1_frac            0        0        0     3750000          0     0  50000         N
 clkin_i2s1                           0        0        0    22579200          0     0  50000         Y

clock i2s1 described in rk3328.dtsi:

	i2s1: i2s@ff010000 {
		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
		...
		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
		clock-names = "i2s_clk", "i2s_hclk";
		...
	};

And now I must set parent for i2s1_pre to clkin_i2s1. Сan anyone help me with this? I tried use assigned-clocks/assigned-clock-parents but unsuccessfull.