October 17, 20241 yr Hello everyone. I want to try to connect a custom AMOLED DSI display with orangepi 3b https://www.phoenixdisplay.com/product/color-displays/oled/at043qhd3008/ And there is practically no information. Maybe someone has seen or encountered similar problems? Do I understand correctly that the dts section on brightness adjustment does not need to be written, because AMOLED as such does not have a backlight? Is it possible to run such a display using simple-panel-dsi? Another interesting question is how to organize the power supply for such a display? It needs different voltages from 1.8 to 4.6 V
December 2, 20241 yr Author Hello everyone I found information that my display works on the driver from sitronix-st7701 I added it to the kernel, rebuilt the kernel and updated (except for the headers) after that I changed dts but there is no reaction. The maximum effect is that an error appears: dw-mipi-dsi-rockchip fe060000.dsi: [drm:dw_mipi_dsi_rockchip_probe] *ERROR* failed to get mipi dphy: -517 It seems I have a problem with how to correctly use ports, endpoints and remote-endpoints. I am currently using fragments port { dsi1_out_port: endpoint { remote-endpoint = <&panel_dsi_in>; }; }; and port { panel_dsi_in: endpoint { remote-endpoint = <&dsi1_out_port>; }; }; but I don't think they are correct. and I also don't see a link in /sys/firmware/devicetree/base/symbols to the new driver and I can't understand if this is correct or not? /dts-v1/; /plugin/; / { fragment@0 { target = <&dsi1>; __overlay__ { status = "okay"; #address-cells = <1>; #size-cells = <0>; port { dsi1_out_port: endpoint { remote-endpoint = <&panel_dsi_in>; }; }; panel_test: panel@0 { compatible = "sitronix, st7701"; reg = <0x0>; status = "okay"; label = "test_display"; VCC-supply = <&vcc_3v3>; IOVCC-supply = <&vcc_3v3>; reset-gpios = <&gpio1 24 0>; // prepare-delay-ms = <2>; // reset-delay-ms = <1>; // init-delay-ms = <20>; // enable-delay-ms = <120>; // disable-delay-ms = <50>; // unprepare-delay-ms = <20>; // dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | // MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; // dsi,format = <MIPI_DSI_FMT_RGB888>; // dsi,lanes = <2>; panel-init-sequence = [ 39 00 06 ff 77 01 00 00 13 39 00 02 ef 08 39 00 06 ff 77 01 00 00 10 39 00 03 c0 63 00 39 00 03 c1 10 02 39 00 03 c2 31 02 39 00 02 cc 10 39 00 11 b0 c0 0c 92 0c 10 05 02 0d 07 21 04 53 11 6a 32 1f 39 00 11 b1 c0 87 cf 0c 10 06 00 03 08 1d 06 54 12 e6 ec 0f 39 00 06 ff 77 01 00 00 11 39 00 02 b0 5d 39 00 02 b1 62 39 00 02 b2 82 39 00 02 b3 80 39 00 02 b5 42 39 00 02 b7 85 39 00 02 b8 20 39 00 02 c0 09 39 00 02 c1 78 39 00 02 c2 78 39 00 02 d0 88 39 ff 02 ee 42 39 00 04 e0 00 00 02 39 00 0c e1 04 a0 06 a0 05 a0 07 a0 00 44 44 39 00 0d e2 00 00 33 33 01 a0 00 00 01 a0 00 00 39 00 05 e3 00 00 33 33 39 00 03 e4 44 44 39 00 11 e5 0c 30 a0 a0 0e 32 a0 a0 08 2c a0 a0 0a 2e a0 a0 39 00 05 e6 00 00 33 33 39 00 03 e7 44 44 39 00 11 e8 0d 31 a0 a0 0f 33 a0 a0 09 2d a0 a0 0b 2f a0 a0 39 00 08 eb 00 01 e4 e4 44 88 00 39 00 11 ed ff f5 47 6f 0b a1 a2 bf fb 2a 1a b0 f6 74 5f ff 39 00 07 ef 08 08 08 40 3f 64 39 00 06 ff 77 01 00 00 13 39 00 03 e8 00 0e 39 00 06 ff 77 01 00 00 00 39 ff 01 11 39 00 06 ff 77 01 00 00 13 39 ff 03 e8 00 0c 39 00 03 e8 00 00 39 00 06 ff 77 01 00 00 00 39 00 02 3a 50 39 ff 01 29 ]; display-timings { native-mode = <&timing0>; timing0: timing-0 { clock-frequency = <30000000>; hactive = <540>; vactive = <960>; hfront-porch = <20>; hback-porch = <20>; hsync-len = <20>; vfront-porch = <20>; vback-porch = <20>; vsync-len = <20>; }; }; port { panel_dsi_in: endpoint { remote-endpoint = <&dsi1_out_port>; }; }; }; }; }; fragment@1 { target = <0xffffffff>; __overlay__ { status = "okay"; }; }; fragment@2 { target = <0xffffffff>; __overlay__ { status = "okay"; }; }; fragment@3 { target = <0xffffffff>; __overlay__ { status = "okay"; }; }; fragment@4 { target = <0xffffffff>; __overlay__ { status = "okay"; }; }; fragment@5 { target = <0xffffffff>; __overlay__ { status = "disabled"; }; }; __fixups__ { video_phy1 = "/fragment@1:target:0"; dsi1_in_vp0 = "/fragment@2:target:0"; dsi1_in_vp1 = "/fragment@3:target:0"; route_dsi1 = "/fragment@4:target:0"; hdmi = "/fragment@5:target:0"; }; };
December 12, 20241 yr Author I've made some progress, and now I'm getting this output in the console. [ 9.712463] rockchip-drm display-subsystem: bound fe070000.dsi (ops 0xffffffc0091f83e8) [ 9.714567] dw_mipi_dsi_rockchip_host_attach+0x34/0xbc [ 9.714577] dw_mipi_dsi_host_attach+0xd4/0xe0 [ 9.714586] mipi_dsi_attach+0x30/0x44 [ 9.714597] st7701_dsi_probe+0x15c/0x160 [ 9.714606] mipi_dsi_drv_probe+0x24/0x30 [ 9.714685] mipi_dsi_driver_register_full+0x64/0x70 [ 9.714698] st7701_dsi_driver_init+0x24/0x30 [ 9.713847] rockchip-drm display-subsystem: [drm] Cannot find any crtc or sizes [ 9.713438] rockchip-drm display-subsystem: failed to parse loader memory [ 9.714009] [drm:drm_atomic_check_only] checking 00000000cb4bca7f [ 9.714034] [drm:drm_atomic_commit] committing 00000000cb4bca7f [ 9.714071] [drm:drm_atomic_state_default_clear] Clearing atomic state 00000000cb4bca7f [ 9.714087] [drm:__drm_atomic_state_free] Freeing atomic state 00000000cb4bca7f [ 9.714201] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/drm_mode_config.c:617 drm_mode_config_validate+0x16c/0x20c [ 9.714256] pc : drm_mode_config_validate+0x16c/0x20c [ 9.714266] lr : drm_mode_config_validate+0x16c/0x20c [ 9.714504] drm_mode_config_validate+0x16c/0x20c [ 9.714515] drm_dev_register+0x38/0x1e8 [ 9.714525] rockchip_drm_bind+0x6dc/0x740 [ 9.714129] Bogus possible_crtcs: [ENCODER:113:DSI-113] possible_crtcs=0x0 (full crtc mask=0x1) [ 9.714201] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/drm_mode_config.c:617 drm_mode_config_validate+0x16c/0x20c [ 9.714208] Modules linked in: [ 9.714229] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.10.160-rockchip-rk356x #1.0.8 [ 9.714235] Hardware name: Rockchip RK3566 OPi 3B (DT) [ 9.714245] pstate: 60c00009 (nZCv daif +PAN +UAO -TCO BTYPE=--) [ 9.714256] pc : drm_mode_config_validate+0x16c/0x20c [ 9.714266] lr : drm_mode_config_validate+0x16c/0x20c The issue seems to be with the CRTC, but I didn’t think that the connection to the CRTC needed to be explicitly defined in the DTS. modetest -M rockchip -s 114@0:480x854 failed to find CRTC for pipe failed to create dumb buffer: Invalid argument
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