I have no need at all for the built in wireless on an Orange Pi Zero board. Is there a way I can disable it entirely to save power? Through the DT or some other means? Thanks!

Make sure that PA20 is LOW, it is the WIFI-POWER-EN.

Would disablign the entry in the DT be enough? I assume that has the entry for the GPIO that controls power to the Wifi unit?

 

Do GPIO default to 'input'? That would leave it floating. Does it need to be actively driven low?

It is good to disable it in the DT, but I presume leaving PA20 floating won't disable power since floating has similar effect to HIGH level on most chips.

Thank you martinayotte! I am working up to being able to help with the SPI driver.

What do you mean about the SPI driver ?

What do you mean about the SPI driver ?

He means mainline u-boot SPI driver - to be able to store environment and use MTD partitions from u-boot proper.

I was interested in improving the read performance of the SPI NOR flash in uboot so that booting kernels is practical.

 

You mentioned the possiblity/need for DMA to get over the 64 byte buffer on the Amlogic SPI driver.

I was interested in improving the read performance of the SPI NOR flash in uboot so that booting kernels is practical. You mentioned the possiblity/need for DMA to get over the 64 byte buffer on the Amlogic SPI driver.

Currently we bypass this limitation using FIFO interrupts, but DMA probably would be faster for large transfers.

I doubt there will be huge performance gain, because even with DMA, there will be some latency for DMA buffer been filled.

When I ported the FIFO large transfer, I said that when I get a chance, I will check the latency with logic analyser, but I didn't got chance yet.

I have a scope that does SPI decode as well as a cheap 24MHz logic analyzer. I haven't done a ton of high speed serial work since the early 90's, but I'm ready to try.

For me "time is the missing ingredient" ...

If you have some spare time, you could check the latency time between the FIFO fills, and also if CS is asserted during the whole large transfer, not only during the FIFO size of 64 bits.

Okay, let me dig out my SMT clip/probes!

I found my SMD clips!  ITT Pomona Model 5514.  They were even where I thought they would be!  Too bad it was at the bottom of a drawer that I don't think I've touched since we moved last.  Nine years ago......

Apologies for the necromancy but this here is relevant!

 

I want to disable Wi-Fi entirely on the OPi0+, from the schematic it appears that PA20 is also responsible for the power to the RTL8189 on that board.

 

Are there any advantages to using the DT to set the GPIO to low as opposed to doing it in userspace through sysfs with mainline kernel? If using DT could anyone point me to a guide for this? I've searched but to no avail.